Which of the following can result from a slow input signal transition?
A) Oscillations may occur on the output of logic gates and inverters.
B) Failure to produce an output signal
C) Erratic triggering of flip-flops
D) Both A and C
E) Both B and C
Question 2
Which of the following statements best describes an asynchronous digital system?
A) It is difficult to design and troubleshoot because the output cannot change states unless a clock input is synchronized to the SET and CLEAR inputs.
B) It is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal.
C) It is easy to design and troubleshoot because the output state is independent of the inputs.
D) It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change.
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