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Author Question: A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the ... (Read 100 times)

Wadzanai

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on: Jul 28, 2018
A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with an oscilloscope reveals the presence of glitches. What might be the source of these glitches?
 
  A) A race condition exists between the Q and Q outputs to the AND gate.
  B) The PRESET and CLEAR terminals may have been left floating.
  C) A race condition exists between the J and K inputs.
  D) A race condition exists between the CLOCK and the outputs of the flip-flop feeding the AND gate.

Question 2

A push-button switch is used to input data to a register. The output of the register is erratic. Which of the following could be the cause of the problem?
 
  A) The power supply is probably noisy.
  B) The register IC is intermittent and failure is imminent.
  C) The socket contacts on the register IC are corroded.
  D) The switch contacts are bouncing.


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sailorcrescent

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Reply #1 on: Jul 28, 2018
Answer to Question 1

D

Answer to Question 2

D


Wadzanai

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Reply 2 on: Jul 28, 2018
Thanks for the timely response, appreciate it

aruss1303

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Reply 3 on: Yesterday
Great answer, keep it coming :)

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