Author Question: The output of an OR gate is connected directly to the input of an AND gate. The other AND gate input ... (Read 232 times)

Haya94 · **on:** Jul 27, 2018

The output of an OR gate is connected directly to the input of an AND gate. The other AND gate input is a constant Enable HIGH. A technician checks the inputs to the OR gate and notes a HIGH and LOW. The output of the OR gate is noted as being a HIGH. The Enable HIGH input to the AND gate is verified as normal. The technician checks the OR gate input to the AND gate and observes a LOW or no voltage condition. Of the probable causes listed, select the one that most likely is the problem. Assume CMOS gates.

A) A short between the OR gate output and the AND gate input
B) A short between the input terminals of the AND gate
C) An internal short in the AND gate
D) An open connection between the OR gate output and the AND gate input

Question 2

Looping on a K-map always results in the elimination of:

A) variables that remain unchanged within the loop.
B) variables within the loop that appear in both complemented and uncomplemented form.
C) variables within the loop that appear only in their complemented form.
D) variables within the loop that appear only in their uncomplemented form.