SLC 500 ladder logic with two cascaded timers ________. A) Has ...

[shofmannx20]

SLC 500 ladder logic with two cascaded timers ________.
 
  A) Has a time delay equal to one timer's delay multiplied by the other timers delay
  B) Has one timer's DN bit enabling another timer's input
  C) Places the cascade timers in series on the ladder rung
  D) None of the above

Question 2

Which one of the following guidelines for troubleshooting indirect and indexed addressing NOT valid?
 
  A) Verify that pointers do not point to addresses outside the memory boundaries.
  B) Use the temporary end (TND) instruction and single scan mode to stop scanning at points in the ladder where addressing indexes can be verified.
  C) Verify that the index value for the address offset in S:24 register has been moved to the register just ahead of the rung where the indexing is performed.
  D) When working on an indexed or indirect addressing mode solution start with a large data base.

[fromAlphatoOmega22]

Answer to Question 1

D

Answer to Question 2

D