A MOD 12 and a MOD 10 counter are cascaded. The input clock ...

[leilurhhh]

A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency.
 
  A) 500 kHz B) 1,500 kHz C) 5 MHz D) 6 MHz

Question 2

A state transition diagram for designing a synchronous nonbinary counter should include:
 
  A) the desired states in the expected sequence as well as the undesired states leading to a desired state.
  B) the desired and the undesired states in any sequence.
  C) the undesired states in their expected sequence as well as the desired in any sequence.
  D) the desired states in any sequence and the undesired states in their expected sequence.

[karmakat49]

Answer to Question 1

A

Answer to Question 2

A

[leilurhhh]

Gracias!

[Joy Chen]

Thanks for the timely response, appreciate it