The output of an AND gate is LOW ________. A) when at least ...

[awywial]

The output of an AND gate is LOW ________.
 
  A) when at least one input is LOW B) only when all inputs are LOW
  C) only when all inputs are HIGH D) None of the above

Question 2

For a negative-logic pulse, the trailing edge is the ________.
 
  A) HIGH-to-LOW transition B) positive-going edge
  C) falling edge D) negative-going edge

[Gabe]

Answer to Question 1

A

Answer to Question 2

B

[awywial]

Thanks

[Gabe]

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