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Author Question: When mapping an SOP expression using a Karnaugh map a 0 is placed in each cell corresponding to the ... (Read 88 times)

ghost!

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on: Jul 28, 2018
When mapping an SOP expression using a Karnaugh map a 0 is placed in each cell corresponding to the value of the product term.
 
  Indicate whether the statement is true or false

Question 2

VHDL and Verilog are examples of ________.
 
  A) logic design standards B) logic simulation tools
  C) schematic entry software D) hardware description languages
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randomguy133

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Reply #1 on: Jul 28, 2018
Answer to Question 1

FALSE

Answer to Question 2

D


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ghost!

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Reply #2 on: Jul 28, 2018
Both answers were spot on, thank you once again


randomguy133

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Reply #3 on: Jul 28, 2018
Great! Please up vote :D


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