When mapping an SOP expression using a Karnaugh map a 0 is placed ...

[ghost!]

When mapping an SOP expression using a Karnaugh map a 0 is placed in each cell corresponding to the value of the product term.
 
  Indicate whether the statement is true or false

Question 2

VHDL and Verilog are examples of ________.
 
  A) logic design standards B) logic simulation tools
  C) schematic entry software D) hardware description languages

[randomguy133]

Answer to Question 1

FALSE

Answer to Question 2

D

[ghost!]

Both answers were spot on, thank you once again

[randomguy133]

Great! Please up vote