In a J-K flip-flop, the SET state occurs when A) J is low, K ...

[theo]

In a J-K flip-flop, the SET state occurs when
 
  A) J is low, K is high, and there is a triggering clock edge.
  B) J and K are low and there is a triggering clock edge.
  C) J is high, K is high, and there is a triggering clock edge.
  D) J is high, K is low, and there is a triggering clock edge.

Question 2

On the typical 14 pin IC, pin 14 is connected to ground.
 
  Indicate whether the statement is true or false

[elyse44]

Answer to Question 1

D

Answer to Question 2

FALSE