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Author Question: In a J-K flip-flop, the SET state occurs when A) J is low, K is high, and there is a triggering ... (Read 48 times)

theo

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on: Jul 28, 2018
In a J-K flip-flop, the SET state occurs when
 
  A) J is low, K is high, and there is a triggering clock edge.
  B) J and K are low and there is a triggering clock edge.
  C) J is high, K is high, and there is a triggering clock edge.
  D) J is high, K is low, and there is a triggering clock edge.

Question 2

On the typical 14 pin IC, pin 14 is connected to ground.
 
  Indicate whether the statement is true or false


elyse44

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Reply #1 on: Jul 28, 2018
Answer to Question 1

D

Answer to Question 2

FALSE


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